This invention relates to electronic digital counter circuits and more particularly to parallel-carry synchronous, binary counter and programmable clock rate divider circuits implemented with field effect transistors (FETs).
Synchronous binary counters of the type having a chain of simultaneously clocked flip-flop stages interconnected with a parallel enable logic circuit are well known in the art for having the advantage of fast response from the time a clock pulse is applied until all flip-flops reach the next state, and of substantially simultaneous state transitions of the flip-flop stages. Such circuits are also useful as clock rate dividers since the output signal from each stage of the counter changes state at a rate which is equal to the clock rate divided by two taken to some integral power. Typical prior art synchronous counter circuits employ a T-type flip-flop in each stage. A T-type flip-flop is one having an enable input which, if held at a predetermined logic level, causes the flip-flop to "toggle," i.e., to have its logic state complemented after each clock pulse. In prior art parallel carry synchronous counters the enable logic circuit which provides the signals to the enable inputs of each T-type flip-flop generally comprise a plurality of AND gates or NOR gates, each associated with a different flip-flop. The enable input of a given flip-flop receives the output from its associated AND gate or NOR gate which in turn receives the outputs from all previous flip-flop in the chain. Consequently, those gates which are associated with flip-flops near the end of the chain have a large number of inputs, or a high "fan-in", and the outputs of those flip-flops near the beginning of the chain have outputs connected to a large number of gates, or a high "fan-out". The maximum fan-in of the logic gates and the maximum fan-out of the flip-flops in a counter increase with the number of stages in the counter. In general, logic circuits with high fan-in or high fan-out have slow operating speeds.
Therefore, owing to the presence of high fan-in gates and high fan-out flip-flops, prior art parallel carry synchronous binary counter circuits have the deficiency in that the maximum clock rates of such circuits decrease rapidly as the number of counter stages is increased.
Another deficiency of the prior art circuits is that they occupy a large area when incorporated in an integrated circuit chip and, therefore, are costly to implement. The large layout areas of prior art circuits are needed to accommodate the numerous transistors in the enable logic circuits with their high fan-in gates and the numerous interconnections from the high fan-out flip-flops. Moreover, unlike asynchronous ripple counters which can have identical stages, prior art synchronous counter circuits do not have the advantage of a simple and compact modular layout on an integrated circuit chip derived from having identical stages.
A prior art solution to the problems of high fan-in gates, high fan-out flip-flops and large layout area in prior art synchronous, binary counters is to utilize a chain-type enable circuit for propagating a logic "1" carry signal as disclosed in U.S. Pat. No. 4,214,173 by J. Popper. The enable circuit in Popper uses an insulated-gate field-effect transistor (IGFET) transmission gate having its conduction channel connected between the enable terminals of successive ones of the flip-flops of the counter stages and its gate connected to the Q output of the flip-flop of the preceding stage. Thus, when the flip-flop of the preceding stage is in the logic "1" state the enable signal which is applied to the enable terminal of that flip-flop is passed to the enable terminal of the flip-flop of the next succeeding stage. When the flip-flop of the preceding stage is in the logic "0" state, the enable signal applied to that flip-flop is blocked from passing to the flip-flops of succeeding stages. However, such prior art chain-type enable circuit is deficient in that an enable signal having a full logic "1" level of V.sub.DD is reduced after passing through an IGFET transmission gate to have a maximum level of V.sub.DD -V.sub.TH, where V.sub.TH is the threshold voltage of the IGFET of the transmission gate. This loss in the enable signal level reduces the current passing capabilities of succeeding transmission gates and results in a slower propagation time for the enable signal than would be the case if the level of the enable signal were not reduced.
Therefore, a need clearly exists for a parallel-carry synchronous, binary counter having an improved chain-type enable circuit which provides faster enable signal propagation.